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ISL3685
TM
Data Sheet
January 2001
File Number
4860.2
2.4GHz RF/IF Converter and Synthesizer
The ISL3685 is a monolithic SiGe half duplex RF/IF transceiver designed to operate in the 2.4GHz ISM band. The receive chain features a low noise, gain selectable amplifier (LNA) followed by a down-converter mixer. An up-converter mixer and a high performance preamplifier compose the transmit chain. The remaining circuitry comprises a high frequency Phase Locked Loop (PLL) synthesizer with a three wire programmable interface for local oscillator applications. A reduced filter count is realized by multiplexing the receive and transmit IF paths and by sharing a common differential matching network. Furthermore, both transmit and receive RF amplifiers can be directly connected to mixers as bandwidth characteristics attenuate image frequencies. The inherent image rejection of both the transmit and receive functions allows this economic advantage. The ISL3685 is housed in a 44 lead MLFP package well suited for PCMCIA board and MINI PCI applications.
Features
* Highly Integrated * Multiplexed RX/TX IF Path prescribes Single IF Filter * Programmable Synthesizer * Gain Selectable LNA * Power Management/Standby Mode * Single Supply 2.7V to 3.3V Operation
Cascaded LNA/Mixer (High Gain)
* Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25dB * SSB Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7dB * Input IP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -12dBm * IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz
Cascaded LNA/Mixer (Low Gain)
* Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9dB * Input P1dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5dBm * IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz
Ordering Information
PART NUMBER ISL3685IR ISL3685IR96 TEMP RANGE (oC) -40 to 85 -40 to 85 PACKAGE 44 Ld MLFP Tape and Reel PKG. NO L44.7x7
Cascaded Mixer/Preamplifier
* Transmit Cascaded Mixer/Preamplifier Gain . . . . . . .25dB * SSB Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . .10dB * Output P1dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4dBm * IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz
Simplified Block Diagram
RX_MX_IN RF_OUT
Applications
* IEEE802.11 1Mbps and 2Mbps Standard * Systems Targeting IEEE802.11, 11Mbps Standard * Wireless Local Area Networks
RX_MX_OUT
H/L
RX_IN
* PCMCIA Wireless Transceivers * ISM Systems
CP_DO INTERFACE REF_IN TXA_OUT
* TDMA Packet Protocol Radios * MINI PCI Wireless Transceivers
PLL MODULE LO_IN
TX_MX_IN
TXA_IN
1
TX_MX_OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright (c) Intersil Americas Inc. 2000 PRISM(R) is a registered trademark of Intersil Americas Inc. PRISM and design is a trademark of Intersil Americas Inc.
ISL3685 Pinout
ISL3685 (MLF) TOP VIEW
RX_MX_OUT+ BIAS2_VCC1 TX_MX_IN+ ITAT_RES2 ITAT_RES1 PTAT_RES PRE_VCC1 37 RX_MX_IN 36
COL_OUT
44 LNA_VCC1 GND RX_IN BIAS1_VCC1 H/L PE2 PE1 TX_VCC1 GND TXA_OUT GND 1 2 3 4 5 6 7 8 9 10 11
43
42 41 40 39
RF_OUT
GND
38
35 34 33 32 31 30 29 28 27 26 25 24 23
RX_MX_OUTTX_MX_INGND RX_LO_DRIVER_VCC1 LO_VCC1 LO_INLO_IN+ TX_LO_DRIVER_VCC1 TX_MX_VCC1 TX_MX_OUT TX_MX_VCC1
12 13 TXA_IN TX_VCC1
14 15 16 17 LE CLK GND DATA
18 REF_BY
19 REF_IN
20 SYN_VCC2
21 CP_VCC2
22 CP_D0
Pin Description
PIN 1 3 4 5 6 7 8 10 12 13 15 16 17 18 NAME LNA_VCC1 RX_IN BIAS1_VCC1 H/L PE2 PE1 TX_VCC1 TXA_OUT TX_VCC1 TXA_IN LE DATA CLK REF_BY Low Noise Amplifier Positive Power Supply. Low Noise Amplifier RF Input, internally DC coupled and requires an external blocking capacitor. A shunt capacitor to ground matches the input for return loss and optimum NF. Bias Positive Power Supply for the LNA and Preamplifier. High or Low Gain Select, controls the LNA high and low gain modes. This pin along with pin PE1 and bit M(0) of PLL_PE determine which of various operational modes will be active. Please refer to the Power Enable Truth Table. This pin along with pin PE2 and bit M(0) of PLL_PE determine which of various operational modes will be active. Please refer to the Power Enable Truth Table. Transmit Amplifier Positive Power Supply, requires a high quality decoupling capacitor and a short return path. Transmit Amplifier Output, internally matched to 50, requires an external DC blocking capacitor. Transmit Amplifier Positive Power Supply. Transmit Amplifier Input, internally AC coupled. Synthesizer Latch Enable, the serial interface is active when LE is low and the serial data is latched into defined registers on the rising edge of LE. Synthesizer Serial Data Input, clocked in on the rising edge of the serial clock, MSB first. Synthesizer Clock, DATA is clocked in on the rising edge of the serial clock, MSB first. Synthesizer Reference Frequency Input Bypass, internally DC coupled and requires an external bypass to ground when REF_IN is used as a Single Ended input, requires an external AC coupling capacitor when used as a differential input. DESCRIPTION
2
ISL3685 Pin Description
PIN 19 20 21 22 23 24 25 26 27 28 29 30 32 NAME REF_IN SYN_VCC2 CP_VCC2 CP_DO TX_MX_VCC1 TX_MX_OUT TX_MX_VCC1 TX_LO_Driver_ VCC1 LO_IN+ LO_INLO_VCC1 (Continued) DESCRIPTION Synthesizer Reference Frequency Input, internally DC coupled and requires an external AC coupling capacitor. Synthesizer Positive Power Supply. Synthesizer Charge Pump Positive Power Supply. Synthesizer Charge Pump Output, feeds the PLL loop filter. Transmit Mixer Positive Power Supply. Transmit Mixer RF output, internal AC coupled and internally matched to 50. Transmit Mixer Positive Power Supply. Transmit LO Driver Positive Power Supply. Local Oscillator Positive Input, internally AC coupled, internally matched to 50 when the LO is driven single ended and the LO_IN- is grounded. Local Oscillator Negative Input, internally AC coupled, differential or single ended capability, ground externally for single ended operation. LO Buffer Positive Power Supply.
RX_LO_DRIVER Receiver LO Driver Positive Power Supply. _VCC1 TX_MX_INTransmit Mixer Negative Input, internally DC coupled, high impedance input. Designed to share a common IF matching network/IF SAW filter with the receive mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. Receive Mixer Negative Output, open collector, high impedance output. Designed to share a common IF matching network/IF SAW filter with the transmit mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. Receive Mixer Positive Output, open collector, high impedance output. Designed to share a common IF matching network/IF SAW filter with the transmit mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. Transmit Mixer Positive Input, internally DC coupled, high impedance input. Designed to share a common IF matching network/IF SAW filter with the receive mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. Receive Mixer RF Input, internally DC coupled and requires external AC coupling as well as RF matching. The recommend network consists of a 3.3pF series capacitor followed by a small series inductance of 1.4nH and then a 1.2nH shunt inductor. The series inductance is best implemented on the PC board using a narrow transmission line inductor. PLL Prescaler Positive Power Supply. Connection to external resistor sets the receive and transmit mixers tail currents, independent of Absolute Temperature. Connection to external resistor sets the receive and transmit mixers tail currents, proportional of Absolute Temperature. Bias Positive Power Supply for the receive and transmit mixers. Connection to external resistor sets the LNA and Preamplifier bias currents, independent of Absolute Temperature. Low Noise Amplifier RF Output, internally AC coupled and internally matched to 50. LNA Collector Output, requires a bypass capacitance which is resonant with the PC board parasitics. A small resistance (20) in series with the main PC board VCC bus is recommended to provide isolation from other VCC bypass capacitors. This ensures the image rejection performance of the LNA is maintained. Circuit Ground Pins (Quantity 6 each).
33
RX_MX_OUT-
34
RX_MX_OUT+
35
TX_MX_IN+
36
RX_MX_IN
37 38 39 40 41 42 44
PRE_VCC1 ITAT_RES1 PTAT_RES BIAS2_VCC1 ITAT_RES2 RF_OUT COL_OUT
All Others
GND
3
ISL3685
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V VCC to VCC Decouple . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V Any GND to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) MLFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (MLF - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85oC Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.3V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Intersil TB379.
General Electrical Specifications 25oC, VCC = 2.7V Unless Otherwise Specified
PARAMETER Supply Voltage Receive Total Supply Current (LNA in High Gain) Receive Total Supply Current (LNA in Low Gain) Transmit Total Supply Current Standby Total Supply Current (PLL and LO Buffers Active) TX/RX Power Down Supply Current (Note 2) TX/RX/Power Down Time (Note 3) RX/TX, TX/RX Switching Time (Note 3) CMOS Low Level Input Voltage CMOS High Level Input Voltage, Any VDD/VCC CMOS High or Low Level Input Current NOTES: 2. Standby current is measured after a long elapsed time (20 seconds). 3. TX/RX/TX switching time and power Down/Up time are dependent on external components. MIN 2.7 0.7*VDD -3.0 TYP 32 25 41 6.5 1 0.2 MAX 3.3 38 32 45 10 100 10 1 0.3*VDD 3.6 +3.0 UNITS V mA mA mA mA A s s V V A
Cascaded LNA/Mixer AC Electrical Specifications
Assumes a direct connection between the LNA and Mixer, IF = 374MHz, LO = 2075MHz at -6dBm, VCC = 2.7 Unless Otherwise Specified, 25oC TEST CONDITIONS MIN 2400 280 1800 TYP 374 -6 25 3.7 -12 -23 -9 25 -58 MAX 2500 600 2220 0 29 5.0 -1 -40 UNITS MHz MHz MHz dBm dB dB dBm dBm dB dB dBc dBm
PARAMETER RF Frequency Range IF Frequency Range LO Frequency Range LO Input Drive Level Power/Voltage Gain Noise Figure SSB Input IP3 Input P1dB Power/Voltage Gain Noise Figure Output IM3 at -12dBm Input Tones Input P1dB
Single End or Differential High Gain Mode
-10 21.5 -17.5 -27.5
Low Gain Mode
-11 -1
4
ISL3685
Cascaded LNA/Mixer AC Electrical Specifications
Assumes a direct connection between the LNA and Mixer, IF = 374MHz, LO = 2075MHz at -6dBm, VCC = 2.7 Unless Otherwise Specified, 25oC (Continued) TEST CONDITIONS High Gain Mode Low Gain Mode LO VSWR (Direct) Differential IF Output Load IF Output Capacitance (Single Ended) IF Output Resistance (Single Ended) LO to LNA Input Feedthrough (Cascaded, no Filter) Gain Switching Speed at Full Scale - High to Low Gain Switching Speed at Full Scale - Low to High Image Rejection (Cascaded, No Filter) 1dB settling 1dB settling With Matching Network LO = Single End Shared with TX MIN TYP 200 1.2 5.5 -65 0.03 0.25 14 MAX 2.0:1 2.0:1 2.0:1 -50 0.1 0.3 UNITS pF k dBm s s dB
PARAMETER LNA Input 50 VSWR with Match Network
Cascaded Transmit Mixer AC Electrical Specifications
Assumes a direct connection between the Mixer and Preamplifier, F = 374MHz, LO = 2075MHz at -6dBm, VCC = 2.7 Unless Otherwise Specified, 25oC. MIN 2400 280 1800 TYP 374 25 10 +14 +4 -6 -25 1.4:1 200 1.1 0.7 MAX 2500 600 2220 29 15 0 3.0:1 2.0:1 UNITS MHz MHz MHz dB dB dBm dBm dBm dBm pF k
PARAMETER RF Frequency Range IF Frequency Range LO Frequency Range Power Conversion Gain SSB Noise Figure Output IP3 Output P1dB LO Input Drive Level LO to Transmit Amp. Output Feedthrough (Cascaded, No Filter) Preamplifier Output 50 VSWR LO 50 VSWR Differential IF Input Load IF Input Capacitance (Single Ended) IF Input Resistance (Single Ended)
TEST CONDITIONS
200 In, 50 Out
21 +12 +2.8
Same as RX
-10 -
LO = Single End Shared with RX
-
Phase Lock Loop Electrical Specifications (See Notes 4 through 12)
PARAMETER Operating LO Frequency (32/33 Prescaler) Operating LO Frequency (64/65 Prescaler) Reference Oscillator Frequency Selectable Prescaler Ratios (P) Swallow Counter Divide Ratio (A Counter) Programmable Counter Divide Ratio (B Counter) Reference Counter Divide Ratio (R Counter) Reference Oscillator Sensitivity, Single or Differential Sine Inputs TEST CONDITIONS MIN 1800 1800 32/33 0 3 3 0.5 TYP MAX 2220 3500 50 64/65 127 2047 32767 VCC UNITS MHz MHz MHz VPP
5
ISL3685
Phase Lock Loop Electrical Specifications (See Notes 4 through 12)
PARAMETER Reference Oscillator Sensitivity, CMOS Inputs, Single Ended or Complementary Reference Oscillator Duty Cycle Charge Pump Sink/Source Current/Tolerance Charge Pump Sink/Source Current/Tolerance Charge Pump Sink/Source Current/Tolerance Charge Pump Sink/Source Current/Tolerance Charge Pump Sink/Source Mismatch Charge Pump Output Compliance Charge Pump Supply Voltage Serial Interface Clock Width High Level tCWH Low Level tCWL Serial Interface Data/Clk Set-Up Time tCS Serial Interface Data/Clk Hold Time tCH Serial Interface Clk/LE Set-Up Time tES Serial Interface LE Pulse Width tEW NOTES: 4. The Serial data is clocked on the Rising Edge of the serial clock, MSB first. The serial Interface is active when LE is LOW. The serial Data is latched into defined registers on the rising edge of LE. 5. As long as power is applied, all register settings will remain stored, including the power down state. The system may then come in and out of the power down state without requiring the registers to be rewritten. 6. CMOS Reference Oscillator input levels are given in the General Electrical Specification section. POWER ENABLE TRUTH TABLE PE1 0 1 1 0 X NOTE: 7. PLL_PE is controlled via the serial interface, and can be used to disable the synthesizer. The actual synthesizer control is a logic AND function of PLL_PE and the result of the logic OR function of PE1 and PE2. PE1 and PE2 directly control the power enable functionality of the LO buffers. PE2 0 1 0 1 X PLL_PE (SERIAL BUS) 1 1 1 1 0 STATUS Power Down State, PLL in Save Mode, Active Serial Interface Receive State Transmit State PLL Inactive, Inactive RX, TX, Active Serial Interface PLL Disabled, Disabled PLL Registers, Active Serial Interface Charge Pump VCC = VCC2 CMOS Inputs 250A Selection 25% 500A Selection 25% 750A Selection 25% 1mA Selection 25% TEST CONDITIONS (Continued) MIN 40 0.18 0.375 0.56 0.75 0.5 2.7 20 20 20 10 20 20 TYP CMOS 0.25 0.50 0.75 1.0 MAX 60 0.32 0.625 0.94 1.25 15 VCC2 -0.5 3.6 UNITS Note 7 % mA mA mA mA % V V ns ns ns ns ns ns
PLL Synthesizer Table
REGISTER DEFINITION SERIAL BITS LSB 1 R Counter A/B Counter Operational Mode 0 0 1 2 0 1 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 MSB
R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) R(9) R(10) R(11) R(12) R(13) R(14) A(0) A(1) A(2) A(3) A(4) A(5) A(6) B(0) B(1) B(2) B(3) M(0) 0 M(2) M(3) M(4) M(5) M(6) M(7) M(8) 0 0 B(4) 0 B(5) 0 B(6) B(7)
X (Don't Care) B(8) B(9) B(10) X X
M(13) M(14) M(15)
6
ISL3685
Reference Frequency Counter/Divider
BIT R(0-14) DESCRIPTION Least significant bit R(0) to most significant bit R(14) of the divide by R counter. The Reference signal frequency is divided down by this counter and is compared with a divided LO by a phase detector.
LO Frequency Counters/Dividers
BIT A(0-6) B(0-11) DESCRIPTION Least significant bit A(0) to most significant bit A(6) of a 7-bit Swallow counter and LSB B(0) to MSB B(10) of the 11-bit divider. The LO frequency is divided down by [P*B+A], where P is the Prescaler divider set by bit M(2). This divided signal frequency is compared by a phase detector with the divided Reference signal.
Operational Modes
BIT M(0) M(2) M(3) M(4) DESCRIPTION (PLL_PE), Phase Lock Loop Power Enable. 1 = Enable, 0 = Power Down. Serial port always on. Prescaler Select. 0 = 32/33, 1 = 64/65. Charge Pump Current Setting M(4) 0 0 1 1 M(5) M(6) Charge Pump Sign M(6) 0 0 M(7) M(8) M(13) LD Pin Multiplex Operation M(13) 0 0 1 1 1 M(14) M(15) Charge Pump Operation/Test M(15) 0 0 1 1 M(5) 0 1 M(8) 0 1 0 1 1 M(14) 0 1 0 1 Normal Operation Charge Pump Constant Current Source Charge Pump Constant Current Sink High Impedance State Source if LO/ [P*B+A] < Ref/R Source if LO/ [P*B+A] > Ref/R M(7) X X X 0 1 OUTPUT AT PIN LD Lock Detect Operation Short to GND Serial Register Read Back Ref. Divided by R Waveform LO Divided by [P*B+A] Waveform OPERATION/TEST M(3) 0 1 0 1 OUTPUT SINK/SOURCE 0.25mA 0.50mA 0.75mA 1.00mA
7
ISL3685
DATA
BIT 20: MSB
BIT 19
BIT 10
BIT 9
BIT 1
BIT 1: LSB
CLOCK tCWL
LE tCS OR tCH tCWH tES LE tEW
NOTES: 8. Parenthesis data indicates programmable reference divider data. 9. Data shifted into register on clock rising edge. 10. Data is shifted in MSB first. FIGURE 1. SERIAL DATA INPUT TIMING
fR
fP
LD
DO
H Z
I L
I
I
fR > fP
fR = fP
fR < fP
fR < fP
fR < fP
NOTES: 11. Phase difference detection range: -2 to +2. 12. The minimum width pump up and pump down current pulses occur at the DO pin when the loop is locked. FIGURE 2. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
8
ISL3685 ISL3685 Evaluation Schematic Diagram
R11 9.53k
R12 C12 0.01F C7 .01F C3 7pF R2 20 R13
1.5k 9.53k C16 0.01F
LNA_OUT C14 0.01F R3 100k LNA_HL R4 100k PE2 GP1 R6 100pF 100 GP2 C29 LNA VCC LNA_IN C4 7pF C5 1pF 0.01F C1 GND RX IN BIAS VCC H/L PE2 PE1 TX VCC2 GND TXA OUT 1 2 3 4 5 6 7 8 9 10 11 C2 7pF
PRE_OUT C10 C9
12 13 14 15 16 17
GP3
7pF
TXA IN GND IF DATA CLK
R5 100k R1 0
NOTES: L23 is 807 mils from edge of SMA pad to center of component pad. C26 is 381 mils from edge of U1 pin 13 to center of pad. R19 is 37 mils from edge of R17 SMA side to center of pad.
C36 .01F
PRE_IN
PREIN C26 1.5pF C19 1000pF C32
LOCATION = GP4 (NO FIT) + 4.7F 0.1F C53 C54 C33 A 7pF
0.56H C6
22pF R8 0
F4106 (NO FIT) REF_IN
R16
0
A
9
0.1F
1.5k L1
(NO FIT)
1 2
C21
VDD 3 ENB OUT GND
R10
C20
4
1000pF
XTAL__VCC (NO FIT)
U6
1000pF
REF BY REF IN SYN VDD CP VDD CP D0
TX VCC1
18 19 20 21 22
PE1
.01
44 43 42 41 40 39 38 37 36 35 34
RF OUT ITAT RES2 BIAS VCC PTATA RES ITAT RES1 PRF VDD RX MX IN TX MX IN+ RX MX OUT+
C8 7pF COI I OUT GND
U1 MLP2 44 PIN PACKAGE
33 32 31 30 29 28 27 26 25 24 23
ISL3685 ISL3685 Evaluation Schematic Diagram (Continued)
77 x 5 MIL TRACE L23 RX_MIX_IN 1.2NH C25 220pF 3.3pF C27 3.3pF R36 0 TI IF_IN/OUT *4 *IF IO
FILTERS VALUES (10kHz DEFAULT) BW C43 C44 R20 1kHz 0.69F 1.5k 649 0.01F 10kHz 0.027F 3.48k 1.74k 330pF 0.068F 2700pF
C17
C31 1.1k 1.1k 3.3pF 39NH L10
R9 0 U4 4 C34 + 4.7F (NO FIT) 0.1F C51 C52 C63 0.01F A C37 + 4.7F OUT IN
R21 C45
39NH
L9
R14
3 0.1F 1 5 4.7F C49 C48 D1 +
VCC_IN
R15
MAX8867 SHDN BP GND 2
0.01F
0.01F
0.01F
C39
C40
C38
33 32 31 30 29 28 27 26 25 24 23
56
C58
TXMXO
1000pF
R MX OUTTX MX INLO GND RX LO DRIVER VCC LO VCC LO INLO IN+ TX LO DRIVER VCC TX MX VCC2+ TX_MX_OUT
220pF C55 10pF R19
C50 0.01F
LOIN R17 560
4 6
TX_MIX_OUT
UPC2745TB 2 3 U3 5 A C56 10pF R34 91 1 R33 82 R35 82
TX_MX_VCC2
U2 2 0.1F 10pF C46 C47 3 VCONT GROUNDS 4 5A 5B 5C 5D R20 1.74k 0.027F 3.48K 330pF C45 C44 ENFVZ5F81 VCC RF
2700pF
C43
R25
R25
20k
20k
U5 47pF C22 10k R29 10k C23 47pF R30 20k 4 + 4.7F 0.1F C61 C62 R28 0.1F 4.7F OUT IN 3 C60 1 5 C57 0.1F C59 +
R21
EXT_VCO
R27
10k
MAX8867 SHDN BP GND 2
DATA CLK
LE GND UP2 N/C UP1 N/C
10
GP5
ISL3685 Typical Performance Curves
VCC = 3.30V RF = 1.7GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK 5 5 3
SCALE 5dB/DIV
1 3 VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
1
Marker 1 = 1.7GHz, Real = 16.7, Imaginary = -31.8 Marker 3 = 2.45GHz, Real = 15.0, Imaginary = -8.0 Marker 5 = 3.0GHz, Real = 16.5, Imaginary = 10.5 FIGURE 3. S11 LNA in HIGH GAIN
Marker 1 = 1.7GHz, 7.0dB Marker 3 = 2.45GHz, 15.3dB Marker 5 = 3.0GHz, 12.5dB FIGURE 4. S21 LNA in HIGH GAIN
SCALE 10dB/DIV
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK 5
1 VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
3
234 5
1
Marker 1 = 1.7GHz, -46.4dB Marker 3 = 2.45GHz, -44.1dB Marker 5 = 3.0GHz, -35.4dB FIGURE 5. S12 LNA in HIGH GAIN
Marker 1 = 1.7GHz, Real = 8.2, Imaginary = -43.5 Marker 3 = 2.45GHz, Real = 39.4, Imaginary = 19.4 Marker 5 = 3.0GHz, Real = -50.6, Imaginary = -45.4 FIGURE 6. S22 LNA in HIGH GAIN
11
ISL3685 Typical Performance Curves
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK 5
(Continued)
SCALE 5dB/DIV
5 3
1 3 5 VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
1
Marker 1 = 1.7GHz, Real = 19.2, Imaginary = -26.1 Marker 3 = 2.45GHz, Real = 16.7, Imaginary = -2.1 Marker 5 = 3.0GHz, Real = 14.1, Imaginary = 15.0 FIGURE 7. S11 LOW GAIN LNA
Marker 1 = 1.7GHz, -12.4dB Marker 3 = 2.45GHz, -18.9dB Marker 5 = 3.0GHz, -15.4dB FIGURE 8. S21 LOW GAIN LNA
SCALE 5dB/DIV
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK
5 3 1
3 5
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
1
Marker 1 = 1.7GHz, -12.4dB Marker 3 = 2.45GHz, -18.9dB Marker 5 = 3.0GHz, -15.7dB FIGURE 9. S12 LOW GAIN LNA
Marker 1 = 1.7GHz, Real = 28.2, Imaginary = -31.7 Marker 3 = 2.45GHz, Real = 32.5, Imaginary = 24.2 Marker 5 = 3.0GHz, Real = 64.7, Imaginary = -12.8 FIGURE 10. S22 LOW GAIN LNA
12
ISL3685 Typical Performance Curves
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30dBm NO MATCH NETWORK
(Continued)
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK
3
5
5 3 1 1
Marker 1 = 1.7GHz, Real = 18.6, Imaginary = -84.7 Marker 3 = 2.45GHz, Real = 13.0, Imaginary = -46.8 Marker 5 = 3.0GHz, Real = 8.0, Imaginary = -25.3 FIGURE 11. S11 RX MIXER
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30dBm NO MATCH NETWORK
Marker 1 = 1.7GHz, Real = 21.0, Imaginary = -54.8 Marker 3 = 2.45GHz, Real = 42.1, Imaginary = 6.4 Marker 5 = 3.0GHz, Real = 54.4, Imaginary = -34.6 FIGURE 12. S22 TX_MIX_OUT
SCALE 5dB/DIV
3
5
3
5 1 VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
1
Marker 1 = 1.7GHz, Real = 7.8, Imaginary = -47.0 Marker 3 = 2.45GHz, Real = 15.4, Imaginary = 7.53 Marker 5 = 3.0GHz, Real = 37.9, Imaginary = -12.5 FIGURE 13. S11 TX PREAMP
Marker 1 = 1.7GHz, 5.6dB Marker 3 = 2.45GHz, 15.6dB Marker 5 = 3.0GHz, 15.3dB FIGURE 14. S21 TX PREAMP
13
ISL3685 Typical Performance Curves
SCALE 10dB/DIV 3 5
(Continued)
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK
3 1 5
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
1
Marker 1 = 1.7GHz, -46.2dB Marker 3 = 2.45GHz, -30.7dB Marker 5 = 3.0GHz, -32.8dB FIGURE 15. S12 TX PREAMP
Marker 1 = 1.7GHz, Real = 7.2, Imaginary = -27.1 Marker 3 = 2.45GHz, Real = 39.5, Imaginary = 2.7 Marker 5 = 31.8, Real = 31.8, Imaginary = -17.2 FIGURE 16. S22 TX PREAMP
TYPICAL APPLICATION, TEMP = 85oC
TYPICAL APPLICATION, TEMP = -40oC 2.7V 3.3V
GAIN 1dB/DIV. NF 1dB/DIV.
2.7V
3.3V
GAIN 1dB/DIV. NF 1dB/DIV.
3.3V
2.7V
3.3V 2.7V GAIN AT CURSOR 14.0dB AT 2.7V, 14.3dB AT 3.3V NOISE FIGURE AT CURSOR 3.9dB AT 2.7V, 3.73dB AT 3.3V RF 2.4GHz RF 2.5GHz GAIN AT CURSOR 16.5dB AT 2.7V, 17.0dB AT 3.3V NOISE FIGURE AT CURSOR 2.64dB AT 2.7V, 2.35dB AT 3.3V RF 2.4GHz RF 2.5GHz
FIGURE 17. LNA HIGH SETTING, GAIN AND NF
FIGURE 18. LNA HIGH SETTING GAIN AND NF
14
ISL3685 Typical Performance Curves
TYPICAL APPLICATION, TEMP = 85oC
(Continued)
TYPICAL APPLICATION, TEMP = -40oC
3.3V GAIN 1dB/DIV. NF 1dB/DIV. 3.3V 2.7V 2.7V GAIN 1dB/DIV. NF 1dB/DIV. 3.3V 2.7V
3.3V
2.7V
GAIN AT CURSOR -19.5dB AT 2.7V, -19.2dB AT 3.3V NOISE FIGURE AT CURSOR 20.2dB AT 2.7V, 19.4dB AT 3.3V RF 2.4GHz RF 2.5GHz
GAIN AT CURSOR -18.6dB AT 2.7V, -18.0dB AT 3.3V NOISE FIGURE AT CURSOR 17.0dB AT 2.7V, 16.3dB AT 3.3V RF 2.4GHz RF 2.5GHz
FIGURE 19. LNA LOW SETTING GAIN AND NF
FIGURE 20. LNA LOW SETTING GAIN AND NF
TYPICAL APPLICATION, TEMP = 85oC GAIN 5dB/DIV. NF 5dB/DIV. 2.7V 3.3V
TYPICAL APPLICATION, TEMP = -40oC GAIN 5dB/DIV. NF 5dB/DIV.
2.7V
3.3V
3.3V
2.7V
3.3V
2.7V
GAIN AT CURSOR 7.5dB AT 2.7V, 7.7dB AT 3.3V NOISE FIGURE AT CURSOR 10.6dB AT 2.7V, 10.0dB AT 3.3V RF 2.4GHz IF 325.000MHz RF 2.5GHz IF 425.000MHz
GAIN AT CURSOR 10.0dB AT 2.7V, 10.1dB AT 3.3V NOISE FIGURE AT CURSOR 10.0dB AT 2.7V, 8.3dB AT 3.3V RF 2.4GHz IF 325.000MHz RF 2.5GHz IF 425.000MHz
FIGURE 21. RX MIXER GAIN AND NF
FIGURE 22. RX MIXER GAIN AND NF
NOISE FIGURE AT CURSOR 8.1dB AT 2.7V, 8.7dB AT 3.3V TYPICAL APPLICATION, TEMP = -40oC
TYPICAL APPLICATION, TEMP = 85oC
3.3V 2.7V GAIN 1dB/DIV. NF 1dB/DIV. 3.3V 2.7V 2.7V 3.3V 3.3V GAIN 1dB/DIV. NF 1dB/DIV.
2.7V
GAIN AT CURSOR 7.7dB AT 2.7V, 7.8dB AT 3.3V NOISE FIGURE AT CURSOR 8.9dB AT 2.7V, 9.0dB AT 3.3V RF 0.365GHz RF 0.385GHz
GAIN AT CURSOR 10.4dB AT 2.7V, 10.9dB AT 3.3V, NOISE FIGURE AT CURSOR 8.1dB AT 2.7V, 8.7dB AT 3.3V RF 0.365GHz IF 2440.000MHz RF 0.385GHz IF 2460.000MHz
FIGURE 23. TX MIXER GAIN AND NF
FIGURE 24. TX MIXER GAIN AND NF
15
ISL3685 Typical Performance Curves
(Continued)
0.5mA/DIV
* *
DEVICE SUPPLY CURRENT (mA)
* * *
VCC = 2.7V VCC = 3.3V
*
VCC = 3.0V ROOM TEMPERATURE = AMBIENT 172ns
-40 -30 -20 -10
0
10
20
30 40 50
60
70 80
90
TEMPERATURE (oC)
FIGURE 25. GAIN SWITCHING SPEED AT FULL SCALE LNA LOW TO HIGH AT BASEBAND
0.5mA/DIV DEVICE SUPPLY CURRENT (mA)
FIGURE 26. RECEIVE TOTAL SUPPLY CURRENT (LNA IN HIGH GAIN)
0.5mA/DIV DEVICE SUPPLY CURRENT (mA)
* * *
* *
* *
VCC = 2.7V VCC = 3.3V
* * *
VCC = 2.7V VCC = 3.3V
*
*
-40 -30 -20 -10
0
10
20
30
40 50
60
70
80 90
-40 -30 -20 -10
0
10 20 30 40
50
60 70 80
90
TEMPERATURE DEGREES oC
TEMPERATURE DEGREES oC
FIGURE 27. RECEIVE TOTAL SUPPLY CURRENT (LNA IN LOW GAIN)
CASCADED LNA/MIXER POWER/VOLTAGE GAIN (dB)
FIGURE 28. TRANSMIT TOTAL SUPPLY CURRENT
0.2dB/DIV CASCADED LNA/MIXER IIP3 (dBm)
0.2dB/DIV
* *
* *
* * *
VCC = 2.7V VCC = 3.3V 0 10 20 30 40 50 60 70 80
*
* *
VCC = 2.7V VCC = 3.3V
*
90 -40 -20 0 20 40 60 80 TEMPERATURE DEGREES (oC)
*
100
-40 -30 -20 -10
TEMPERATURE DEGREES (oC)
FIGURE 29. POWER/VOLTAGE GAIN HIGH GAIN MODE
FIGURE 30. INPUT IP3 HIGH GAIN MODE
16
ISL3685 Typical Performance Curves
0.1dB/DIV CASCADED LNA/MIXER IP1dB (dBm)
(Continued)
CASCADED LNA/MIXER POWER/VOLTAGE GAIN (dB)
* *
0.2dB/DIV
* *
*
* *
* *
-40 -20 0 20 40 60
VCC = 2.7V VCC = 3.3V 80 100
* *
VCC = 2.7V VCC = 3.3V 0 10 20 30
*
40 50 60 70 80 90
TEMPERATURE DEGREES (oC)
-40 -30 -20 -10
TEMPERATURE DEGREES (oC)
FIGURE 31. INPUT P1dB HIGH GAIN MODE
FIGURE 32. POWER/VOLTAGE GAIN LOW GAIN MODE
* CASCADED LNA/MIXER IM3 (dBc) 0.5dB/DIV
* CASCADED LNA/MIXER IM3 (dBc)
1.0dB/DIV
*
*
* *
VCC = 2.7V VCC = 3.3V
* * *
* *
VCC = 2.7V VCC = 3.3V
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE DEGREES (oC)
-40 -30 -20 -10
0
10
20 30
40
50 60
70 80
90
TEMPERATURE DEGREES (oC)
FIGURE 33. RX OUTPUT IM3 AT -5dBm INPUT TONES
FIGURE 34. RX OUTPUT IM3 AT -12dBm INPUT TONES
CASCADED LNA/MIXER LO FEEDTHROUGH (dBm) 0.2dB/DIV
*
CASCADED LNA/MIXER IP1dB (dBm)
0.1dB/DIV
*
*
* *
* *
* *
VCC = 2.7V VCC = 3.3V 0 10 20 30 40 50 60 70 80
*
-40.0 -20 0 20 40
* *
VCC = 2.7V VCC = 3.3V
*
90
*
60 80 100 TEMPERATURE DEGREES (oC)
-40 -30 -20 -10
TEMPERATURE (oC)
FIGURE 35. INPUT P1dB LOW GAIN MODE
FIGURE 36. LO TO LNA INPUT FEEDTHROUGH (CASCADED, NO FILTER)
17
ISL3685 Typical Performance Curves
CASCADED TRANSMITTER/MIXER GAIN (dB)
(Continued)
CASCADED TRANSMITTER/MIXER OIP3 (dBm)
0.2dB/DIV
0.2dB/DIV
* *
*
* * *
VCC = 2.7V VCC = 3.3V 0 10 20
* * *
VCC = 2.7V VCC = 3.3V
*
*
30 40 50 60 70 80 90
*
0 10 20 30 40 50 60 70 80 90 TEMPERATURE DEGREES (oC)
-40 -30 -20 -10
-40 -30 -20 -10
TEMPERATURE DEGREES (oC)
FIGURE 37. POWER CONVERSION GAIN
CASCADED TRANSMITTER/MIXER OP1dB (dBm)
FIGURE 38. OUTPUT IP3
0.2dB/DIV CASCADED TRANSMITTER/ MIXER LO FEEDTHROUGH (dBm)
0.2dB/DIV
* *
*
* * *
VCC = 2.7V VCC = 3.3V 0 10 20 30 40 50 60 70
*
* 80 90
-40 -30 -20 -10
*
* *
40 60
VCC = 2.7V VCC = 3.3V 80 100
TEMPERATURE DEGREES (oC)
-40
-20
0
20
TEMPERATURE DEGREES (oC)
FIGURE 39. OUTPUT P1dB
FIGURE 40. LO TO TRANSMIT AMP OUTPUT FEEDTHROUGH (CASCADED, NO FILTER)
18
ISL3685 Micro Lead Frame Plastic Package (MLFP)
2X A D D/2 D1 D1/2 2X 6 0.50 DIA. 1 2 3 N E1/2 E1 E/2 E 0.25 C B 0.25 C A
L44.7x7
44 LEAD MICRO LEAD FRAME PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VKKD-1 ISSUE A) INCHES SYMBOL A A1 A2 A3 b D D1 MIN MAX 0.039 0.002 0.031 MILLIMETERS MIN MAX 1.00 0.05 0.80 0.20 REF 0.18 0.30 5 NOTES
0.008 REF 0.007 0.012
0.275 BSC 0.265 BSC 0.130 -
7.00 BSC 6.75 BSC 3.30 7.00 BSC 6.75 BSC 3.30 0.50 BSC 0.50 44 11 11 0.75 2 3 3 0.60 12 7 7
0.20 C B 2X 0.20 C A 2X 0 A2 A C 0.05 C SEATING PLANE SIDE VIEW 5 4X P b D2 0.10 M C A B 7 D2/2 N 4X P 1 2 3 E2 7 L e (Nd-1)Xe REF. BOTTOM VIEW C L 5 A1 b C L E2/2 (Ne-1)Xe REF. A3 A1 TOP VIEW B
D2 E E1 E2 e L N Nd Ne P
0.275 BSC 0.265 BSC 0.130
0.019 BSC 0.019 44 11 11 0.009 0.024 12 0.029
0.24 -
CC
Rev. 1 8/00 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd is the number of terminals in the X direction, and Ne is the number of terminals in the Y direction. 4. Controlling dimension: Millimeters. Converted dimensions to inches are not necessarily exact. Angles are in degrees. 5. Dimension b applies to the plated terminal and is measured between 0.20mm and 0.25mm from the terminal tip. 6. The Pin #1 identifier exists on the top surface as an indentation mark in the molded body. 7. Dimensions D2 and E2 are the maximum exposed pad dimensions for improved grounding and thermal performance.
SECTION "C-C" e TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE e
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at website www.intersil.com/quality/iso.asp.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 19

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